Posit number format

Overview

A posit is a fixed-width encoding of real numbers, used here in place of float or fixed-point values for the tensors of a model. The setting the paper tunes is the exponent size es. In MinUn it is chosen per bit width before the bitwidth search runs, and the paper's numbers depend on that choice 2210.16556 §4.1.1 alg. 1.

Each tensor uses a single bitwidth for all its elements, so the compiler does not track bits per element 2210.16556 §1. The posit experiments pair 8 bits with 16 bits as the low and high widths 2210.16556 §4.1 2210.16556 §6.5.

Only one wikillm paper uses posits, so this page covers one design, not a survey of posit hardware or libraries. Other formats appear in the paper only as baselines.

Variants

Only one variant is documented, with two parameters.

Posit 8/16 with a per-tensor bitwidth search (MinUn)

Each tensor is stored at 8 or 16 bits, and a search decides which tensors move to the higher width under a RAM limit 2210.16556 §4.1. The exponent size is set first: 0 or 2 for the 8-bit format, and 1 or 2 for the 16-bit format, each picked by measured accuracy 2210.16556 §5 alg. 1. Card: MinUn: Accurate ML Inference on Microcontrollers.

The paper reports this configuration on SqueezeNet at 54.81% accuracy and 1.16 MB peak RAM, against 55.02% and 4.42 MB for float32. The same table gives 48.33% at 2.21 MB for Shiftry's 8/16-bit fixed-point scheme 2210.16556 §6.7.

Posit widths other than 8 and 16

The paper tried 9-, 10-, 12- and 32-bit posits, but the posit library it used offered only es = 2 for these widths. That choice is a library limit, not a tuned setting 2210.16556 §5. The paper also tried more bitwidth options for posits and reports no measurable gain from them [arxiv:2210.16556 §6.8.2]. Treat these widths as untested beyond the library default.

When to use which

The paper's posit results come from microcontroller-sized models. The constraints below are the ones the paper's evidence supports.

The posit RAM numbers in the appendix are not a format-only comparison. The MinUn posit configuration can store some tensors at 8 bits, while the half-precision and bfloat16 baselines use 16 bits throughout [arxiv:2210.16556 app. D] §4.1. The table does not separate the format from the per-tensor width choice. Ratios computed from the table, posit RAM against the 16-bit baselines, range from about 1.4x (FastGRNN DSA-19) to 4x (Bonsai CR-2).

Implementation sketch

Our reading of the paper's text. The exponent size is fixed first, then the bitwidth search runs. The full search loop is on the MinUn card, 2210.16556 alg. 2-5.

# Choose the posit exponent size per width  [arxiv:2210.16556 §4.1.1] [alg. 1]
# Input:  model, calibration inputs, accuracy function
# Output: es_8 for the 8-bit posit, es_16 for the 16-bit posit

def fit_posit_es(model, inputs):
    # Allowed sizes: 0 or 2 at 8 bits, 1 or 2 at 16 bits  [§5]
    es_8 = best_by_accuracy([0, 2], lambda es: accuracy(model, inputs, 8, es))
    # Keep the candidate with the higher measured accuracy  [§5]
    es_16 = best_by_accuracy([1, 2], lambda es: accuracy(model, inputs, 16, es))
    return es_8, es_16

The paper does not say how ties between exponent sizes are broken.

Pitfalls

• Exponent size is a library choice for other widths. Only es = 2 was available for 9-, 10-, 12- and 32-bit posits 2210.16556 §5.
• The code link is not verified. The paper names a branch of a repository 2210.16556 §1. Its contents could not be read, so every posit detail here rests on the paper text. See the card's paper-vs-code section.
• The accuracy target is a design target. The paper picks the posit configuration per dataset so that accuracy stays within 0.2% of float32 2210.16556 §6.4. This is a selection rule, not a result.
• No variance is reported. All figures are single values [arxiv:2210.16556 §6.4].

Contradictions

• Size of the face-model RAM reduction. The introduction states a drop from about 600 KB to about 180 KB 2210.16556 §1. The appendix gives 614K to 192K for posit Face-B 2210.16556 app. D. The two sets of numbers are not reconciled in the paper.
• Posit RAM reduction against 16-bit baselines. The text reports a reduction of 2.9x to 5.1x, including against half precision and bfloat16 2210.16556 §6.4. The appendix table gives smaller ratios for the same baselines, about 1.4x to 4x by our calculation [arxiv:2210.16556 app. D]. We have not resolved this.

Papers

• MinUn: Accurate ML Inference on Microcontrollers: posit 8/16 storage with per-tensor bitwidth search, exponent size chosen per width, and an exact-cover memory layout for microcontrollers.